About me
My expertise centers on C++ and Python, focusing on Performance Modelling and Kernel development. I also explore Rust and CUDA at a hobbyist level, expanding my understanding beyond my professional experience. Driven by the challenge of enhancing system performance, I aim to achieve this better superior architectural designs and sound software practices.
I’m always keen to learn more about emerging trends in computer architecture and software development.
Experiences
Hanwha Vision subsidiary - A company that ceased activities due to funding constraints at the parent organization.
- Led development of ISA specification API repository, enhancing cross-project compatibility in the Neubla ecosystem.
- Implemented multi-version ISA support in Instruction Set Simulator, integrating checkpoint functionality for state preservation.
- Designed new Neubla RISC-V intrinsic to reduce encoding errors and improve code reliability.
Software Engineer, developed C++ functional models of now cancelled product Intel Tofino network switches.
- Led the development of trace functionality for legacy Tofino chips, ensuring seamless hardware unit execution mapping with customer-provided P4 scripts.
- Modernized legacy code by migrating it to the C++17 standard, enhancing code maintainability and operational efficiency.
- Development of a C++ functional model for ternary content-addressable memory (TCAM), aligning with design specifications.• Led the development of trace functionality for legacy Tofino chips, ensuring seamless hardware unit execution mapping with customer-provided P4 scripts. • Modernized legacy code by migrating it to the C++17 standard, enhancing code maintainability and operational efficiency. • Development of a C++ functional model for ternary content-addressable memory (TCAM), aligning with design specifications.
Verification Engineer. The main programming languages are C++ and Python. My current responsibilities are:
- Modeling parts of an IPU in C++ to test the RTL if meets the specification of the architecture.
- Creating a packet generator in Python to simulate IPU packet transactions so it can be used for the C++ model and the RTL.
- Contribute to the design specification of upcoming chips.
Internship after graduating and before starting my career at Graphcore. During my time at QLM I have accomplished the following:
- Optimized existing Matlab code 80x speed up by rewriting it in Julia combined with calls to C functions and utilizing parallel programming.
- Created tools and libraries for the host machine to communicate with an FPGA.
- Provided better workflow for the company with version control using Git, writing documentation, and using open source languages and tools.
From Jan 2018 to Sep 2018 I was working full-time at Toshiba as Research Engineer in Machine learning as part of my undergraduate degree. Afterward, I have worked part-time while completing my degree.
- Invented and filed a patent of a system that reduces network traffic by 60% of Distributed Neural Networks by using Reinforcement Learning.
- Used machine learning libraries such as Tensorflow on Embedded devices like NVIDIA Jetson to simulate IoT networks.
- Produced demos using JavaScript and ReactJS so they can be used for general meetings and conferences.